FAIR

This project aims to develop a secure and high-performance processor, along with accompanying tools, to counter fault injection attacks targeting embedded devices (smart cards, smartphones, etc). The goal is to overcome the limitations of "lockstep" processors and current Instruction Set Randomization (ISR) schemes, which are often inefficient in terms of performance and energy. In the state of the art, the proposed solutions attempt to adapt already existing tools (cryptographic primitives, instruction sets) to this problem. In contrast, we advocate the need to develop new tools specifically for this use case. First, current cryptographic schemes for ISR suffer from primitives and modes with high latency, as they were designed for other uses. Our first approach, therefore, is to develop a specific primitive and mode to ensure low-latency cryptographic integrity. Second, resilience and integrity of the microarchitecture must scale to larger cores. Hence, we are targeting a CVA6 core. Finally, we must acknowledge that modifying the instruction set can lead to security gains. For this, we propose modifying the RISC-V instruction set to remove the possibility of forward indirect jumps, allowing for a simpler cryptographic scheme and enabling the compiler to efficiently and precisely determine the control flow graph of our application.