EFT-SAFE3A

Up to now, the impact on ICs of Electrical Fast Transient (EFT) stress at system level is not well characterized, but with the recent evolution of semiconductor manufacturer requirements, transient induced IC failure becomes an important concern. This is mainly due to the drastic dimension shrinking and the large number of applications with embedded electronics in severe environments. Transient electrical phenomena are powerful sources of interferences that can cause electronic systems to reset, lose data, or fail to operate and reduce electronic systems reliability. This is even more critical for the aeronautical and automotive applications where people safety depends on the reliability of electronic systems. At equipment level, two phenomena occur due to fast transient electrical stress. The first effect is a complete destruction of the device. This kind of issue is generally solved by a modification of the layout and/or of the protection schemes. But, the implemented methodology demonstrates a lack of management of safety margins and generates time to market delay and additional cost due to redesigns. The second effect consists in malfunctions such as reset or latch up, also called functional robustness. The analysis of such defects is generally more difficult and the way to correct them is not an easy task. Nowadays, the state-of-the-art exhibit that there are no robust methodologies, models and tools allowing the design of products that would result in hardening a system for a certain requirement, whereas managing at the same time the safety margin. Today the design of embedded electronics is based on expertise knowledge and experimental trial and error process. Although, E-SAFE ANR project has defined a first methodology for measurement and simulation, the project was meanly dedicated to ESD induced fatal failures. The results of this project were proposed at the ESD Association (ESDA) committee standards and a discussion group led by LAAS-CNRS has been setup to standardize this work. Functional robustness is not addressed yet and is the next challenge to ensure reliability of equipment with embedded electronics. With the recommendation the ANR did at the end of the project, we expect with this new project to provide a significant breakthrough in the field of system design methodology for improved robustness and reliability. The types of stress addressed within this project are ESD and Short Time EOS, in the range of some microsecond. Using real application scenarios (with different ICs, protection schemes, layout strategies), specific PCBs developed by VALEO and NEXIO, we propose to develop a behavioral modeling approach based on the experimental characterization of the IC for destructive aspect in a first step and for functional robustness in a second one. Experimental validation of the models will be carried out in tight cooperation with the industrial partners. For this purpose, both the strong experience in modeling and measurement techniques proposed by LAAS-CNRS and the measurement and simulation approaches based on the system requirements implemented by the industrial partners will be confronted and combined. The final objective of the project is to build a common system methodology from the bare die to the PCB and the equipment so as to increase development speed, and system safety at first run. More than a model library, we expect to have at the end of the project a clear methodology to extract models for discrete power delivery network (PDN) or integrated circuits, based on new techniques (if needed) or not. We suggest not restricting the modeling language selection, and to work more on the description of the model content itself than on a language implementation. This will allow delivering a design tool-kit (both at ICs and PCB levels) that could help designers product high-safety systems at first pass.