AATLAS

NP-Hard combinatorial optimization problems suffer from an exponential growth in complexity with problem size. They are frequently encountered in many engineering fields, such as planning and scheduling in manufacturing, wire-length optimization, layout, and design partitioning in microelectronic/VLSI design. AATLAS proposes an innovative approach to solve NP-hard problems, bringing together complementary expertise from three partners: IRL 2958 GeorgiaTech-CNRS (GT-CNRS), CentraleSupélec (CS), and Institut Jean Lamour (IJL). The objective is to develop an energy-efficient, reconfigurable, scalable, and integrated optimization solver based on hybrid analog/digital field programmable arrays. The proposed architecture will combine: (i) fully analog computing cores, based on field-programmable analog array (FPAA) platforms, with (ii) pre- and post-processing layers implemented on field-programmable gate arrays (FPGA). AATLAS will reach this objective by implementing three work packages: 1) Combine FPAA and FPGA platforms in an energy-efficient hybrid architecture (IJL), 2) Develop Ising/Hopfield machine based on this architecture (GT-CNRS), 3) Apply Ising/Hopfield machines to large-scale NP-hard problems (CS). Contrary to other computing engines based on physical systems, the FPAA core, while being analog, benefits from the same advantages as its digital counterpart (i.e. FPGA), namely integration, analog reconfigurability, and continuous-valued inter-connection weighting. The hybrid analog-digital system implemented in AATLAS will demonstrate the promises of reconfigurable analog computing for solving large-scale NP-hard problems using physics-inspired energy relaxation techniques.