I_LEGO

The I_LEGO project aims building a consortium able to efficiently answer to the H2020 ICT-06-2019 –Unconventional Nanoelectronics call. Before the call deadline, 28/03/2019, the I_LEGO partners (IMEC, IMS, ECL-INL, LAAS,NAMLAB), led by Professor Cristell Maneux, team leader with 20 years’ experience in advanced and emerging device compact modelling, will persuade major industrial actors to step in the consortium: IBM, GlobalFoundries and Samsung. The LEGO project should, at least, include them in an advisory board to benefit from the industrial vision. Already, the I_LEGO project gather complementary skills in the fields of (i) vertical n- and p- NanoWire Field Effect based 3D-transistors fabrication, (ii) compact modelling of emerging devices, (iii) design of innovative architectures based on emerging technologies, (iv) design of test chips for 3D system integration. Such a gathering is particularly efficient to achieve innovative logic circuit demonstrators based on arrays of vertical nanowire-based transistors. This technology is considered to be the prime candidate for scaling beyond the 7nm gate-length node, but no circuit-scale demonstrations have yet been achieved. Therefore, we propose to: - Develop ground-breaking stacked vertical n- and p- NanoWire Field Effect Transistor technology, - Develop compact models and full design kit (PDK) to support the circuit design process, - Design, build and test 3D logic blocks based on stacked regular fabrics of vertical NWFETs and prove enhanced logic functionality and logic circuit operation, - Assess the technology roadmap improvements and associated logic architecture performance metrics. This disruptive design-technology co-optimization is particularly relevant to answer the ICT-06-2019 –Unconventional Nanoelectronics. In particular, regarding the viability of new approaches to computing components. The I_LEGO project will demonstrate new concepts at transistor and circuit level which bring the potential of highly improved performance for generic applications. Indeed, today, the acceptability of new logic paradigms based on emerging technologies is hindered by the lack of proof that such approaches actually work. The I_LEGO project will deliver proof for monolithic 3D stacks of vertical NWFET to address challenges of compactness, heat dissipation, reduced interconnect length. The very aim being the demonstration of functionality at circuit level by integrating the adequate functional blocks. Hence, the circuit-level research will target a 4-bit ALU through the actual implementation of two logic styles that are well suited to regular fabrics of vertical NWFETs: - majority inverter graphs (MIG) using multiple electrode NWFETs - pass-transistor logic (PTL) using uniform and hybrid n/p NWFETs Huge gains in silicon area are expected through the combination of extremely small elementary device footprint and minimal device usage with MIG and PTL design styles. For example, a 1-bit full-adder can be built in PTL with just 3 vertical hybrid n/p nanowires instead of 31 nanowires in standard logic, and a 1-bit multiplexer can be built in PTL with 1 single vertical uniform nanowire instead of 10 nanowires in standard logic. Such 10x reductions in complexity will lead to similar gains in energy consumption and delay. This will, without doubt, encourage and stimulate large-scale European research institutes and companies to re-invest in this advanced beyond-CMOS emerging technology and to apply real design-technology co-optimization techniques. Finally, the direct outcome of the I_LEGO project is expected to lead to a breakthrough in the field of logic devices and circuits. This will be achieved by implementing and assessing real demonstrators which is directly associated with the objectives of the NEREID project (NanoElectronics Roadmap for Europe: Identification and Dissemination) in term of Beyond CMOS technology and Advanced Logic and connectivity.