PUMA

The PUMA project sets clear and measurable main objectives to reach a TRL 5 from TRL 3 as follows: 1. Define future FPGA requirements for high performance space applications. 2. Provide benchmark to assess technology requirements 3. Define future FPGA architecture to meet applications requirements 4. Design of all FPGA architecture building blocks taking into consideration performance requirements 5. Test chip to validate reliability and radiation hardening performance of 7nm FinFET